AMBA AXI4-Lite

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AMBA AXI4-Lite#

Implements the bus decoder using an AMBA AXI4-Lite CPU interface.

The AXI4-Lite CPU interface comes in two i/o port flavors:

SystemVerilog Interface

  • Command line: --cpuif axi4-lite

  • Interface Definition: axi4lite_intf.sv

  • Class: peakrdl_busdecoder.cpuif.axi4lite.AXI4LiteCpuif

Flattened inputs/outputs

Flattens the interface into discrete input and output ports.

  • Command line: --cpuif axi4-lite-flat

  • Class: peakrdl_busdecoder.cpuif.axi4lite.AXI4LiteCpuifFlat

Protocol Notes#

The AXI4-Lite adapter is intentionally simplified:

  • AW and W channels must be asserted together for writes. The adapter does not support decoupled address/data for writes.

  • Only a single outstanding transaction is supported. Masters should wait for the corresponding response before issuing the next request.

  • Burst transfers are not supported (single-beat transfers only), consistent with AXI4-Lite.

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