Exporter API

Exporter API#

If you are not using the PeakRDL command-line tool, you can still generate busdecoders programmatically using the exporter API:

class peakrdl_busdecoder.BusDecoderExporter(**kwargs: Unpack[ExporterKwargs])#
export(node: RootNode | AddrmapNode, output_dir: str, **kwargs: Unpack[ExporterKwargs]) → None#
Parameters:

  • node (AddrmapNode) – Top-level SystemRDL node to export.

  • output_dir (str) – Path to the output directory where generated SystemVerilog will be written. Output includes two files: a module definition and package definition.

  • cpuif_cls (peakrdl_busdecoder.cpuif.CpuifBase) – Specify the class type that implements the CPU interface of your choice. Defaults to AMBA APB4.

  • module_name (str) – Override the SystemVerilog module name. By default, the module name is the top-level node’s name.

  • package_name (str) – Override the SystemVerilog package name. By default, the package name is the top-level node’s name with a “_pkg” suffix.

  • address_width (int) – Override the CPU interface’s address width. By default, address width is sized to the contents of the busdecoder.

  • cpuif_unroll (bool) – Unroll arrayed addressable nodes into separate instances in the CPU interface. By default, arrayed nodes are kept as arrays.

  • max_decode_depth (int) – Maximum depth for address decoder to descend into nested addressable components. A value of 0 decodes all levels (infinite depth). A value of 1 decodes only top-level children. A value of 2 decodes top-level and one level deeper, etc. By default, the decoder descends 1 level deep.

Example#

Below is a simple example that demonstrates how to generate a SystemVerilog implementation from SystemRDL source.

from systemrdl import RDLCompiler, RDLCompileError
from peakrdl_busdecoder import BusDecoderExporter
from peakrdl_busdecoder.cpuif.axi4lite import AXI4Lite_Cpuif
from peakrdl_busdecoder.udps import ALL_UDPS

input_files = [
    "PATH/TO/my_register_block.rdl"
]

# Create an instance of the compiler
rdlc = RDLCompiler()

# Register all UDPs that 'busdecoder' requires
for udp in ALL_UDPS:
    rdlc.register_udp(udp)

try:
    # Compile your RDL files
    for input_file in input_files:
        rdlc.compile_file(input_file)

    # Elaborate the design
    root = rdlc.elaborate()
except RDLCompileError:
    # A compilation error occurred. Exit with error code
    sys.exit(1)

# Export a SystemVerilog implementation
exporter = BusDecoderExporter()
exporter.export(
    root, "path/to/output_dir",
    cpuif_cls=AXI4Lite_Cpuif
)
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